1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of fabricating a silicide structure.
2. Description of the Related Art
The interconnections between circuit structures in a semiconductor device frequently require the fabrication of contact structures. Where the circuit structures are implemented in silicon, as is commonly the case for impurity regions or gate electrodes, the interfaces between such circuit structures and the contacts typically exhibit relatively high series sheet resistances. The resistances can lead to undesirably high power consumption and lower circuit performance in integrated circuits. One method in use for years to reduce the series resistance of these types of structural interfaces involves the fabrication of metal-silicide layers on sources and drains, and on gate electrodes where polysilicon is the material of choice. Self-aligned silicidation (xe2x80x9csalicidationxe2x80x9d) is perhaps the most common application of this method.
In conventional salicidation, a metal capable of reacting with silicon, such as titanium or cobalt, is deposited on the gate, the sidewall spacers, if any, and the impurity or source/drain regions. A one or two step anneal is performed to react the metal with the polysilicon of the gate and the silicon of the source and drain regions to form silicide. Following the anneal, an etch is performed to remove any unreacted metal.
The improvements in sheet resistance due to silicidation are dependent upon the quality of the silicide film. Film quality is, in-turn, largely a function of film geometry. Wider and thicker silicide films generally have lower resistance. Moreover, wider silicide films lessen the chances that a misaligned contact structure will fail to make contact directly with the underlying silicon or polysilicon. Titanium silicide reactions tend to be self-limiting in the vertical direction. Thus, titanium-silicide films often form to a shallower depth in a silicon substrate than desired. Lateral titanium silicide growth on polysilicon gates is similarly limited. In many cases, a titanium silicide film will only form on two thirds of the width of a poly gate. Cobalt exhibits fewer growth kinetics limitations than titanium. With either material, higher anneal temperatures can lessen the growth kinetics limitations, but at a cost in terms of thermal budget consumption. Furthermore, higher temperatures can cause localized deep silicide penetration that can lead to pn junction penetration.
One limitation on growth kinetics is thought to arise from the topography of the silicon-to-refractory metal interface. If the surface area of the underlying silicon or polysilicon structure could be increased, the silicide reaction rate should increase and result in more extensive silicide films.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of fabricating a silicide film is provided that includes providing a silicon surface and etching the silicon surface at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide.
In accordance with another aspect of the present invention, a method of fabricating a circuit device is provided that includes providing a silicon surface, forming a gate electrode stack on the substrate and forming sidewall spacers adjacent to the gate electrode stack. The silicon surface is etched at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide.
In accordance with another aspect of the present invention, a method of fabricating a circuit device is provided that includes providing a silicon surface, forming a gate electrode stack on the silicon surface and forming a first pair of sidewall spacers adjacent to the gate electrode stack. A second pair of sidewall spacers is formed adjacent to the first pair of sidewall spacers. The silicon surface is etched at between isotropic and anisotropic etching conditions to define a plurality of oblique surfaces thereon and thereby increase the surface area of the silicon surface. A silicide-forming material is deposited on the plurality of oblique surfaces and the silicon surface is heated to react the silicide-forming material therewith and form silicide.